Reference Design

Isolation Design Flow + Dynamic Function eXchange Example Application Note (XAPP1361)

Document ID
XAPP1361
Release Date
2024-05-23
Revision
1.2 English

This reference design is created using the Vivado Design Suite 2021.1 and the Vitis Unified Software Development Platform 2021.1. This design is verified against 2021.1, 2021.2, and 2022.1 versions. Download the reference design files for this application note from the AMD website. The reference design files contains RTL source code for the design, and the C files for the Vitis application.

Reference Design Matrix

The following checklist indicates the procedures used for the provided reference design.

Table 1. Reference Design Matrix
Parameter Description
General
Developer name Satya Pitaka
Target devices Zynq UltraScale+ Devices
Source code provided? Yes
Source code format (if provided) C, Tcl, HDL, Verilog
Design uses code or IP from existing reference design, application note, third party or Vivado software? If yes, list. Yes, design reuse (Lab 7) from Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)
Hardware Verification
Hardware verified? Yes
Platform used for verification ZCU102 Evaluation Board