IDF + DFX

Isolation Design Flow + Dynamic Function eXchange Example Application Note (XAPP1361)

Document ID
XAPP1361
Release Date
2024-05-23
Revision
1.2 English

The Isolation Design Flow (IDF) and Dynamic Function eXchange (DFX) are two production solutions from AMD. They have been available for Zynq UltraScale+ devices from Vivado 2018.3 and later. From Vivado 2020.2 and later, AMD supports the combined flow of IDF and DFX. The document is written with the assumption that the reader is familiar with both IDF and DFX methodologies. Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335), Isolation Design Example for Zynq Ultrascale+ MPSoC Application Note (XAPP1336), Vivado Isolation Verifier User Guide (UG1291), Vivado Design Suite User Guide: Dynamic Function eXchange (UG909), Block Design Containers in Chapter 5 of the

Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) and Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947) for details on these individual methodologies. With this combined support, the user can create nested isolated modules (IM) inside of a reconfigurable partition (RP).

IDF+DFX is enabled by default for all AMD Zynq™ UltraScale+ MPSoC designs, there is no special param needed to enable combined flow. You need to set a param to enable the appropriate set of design rule checks for IDF+DFX. To enable IDF+DFX DRCs, set the following parameter in Vivado:

 set_param hd.enableIDFDRC 1
Note: From Vivado 2021.1 onwards, to enable the IDF DRCs there is no need to set hd.enableIDFDRC param. IDF DRCs are enabled automatically by the tool when the tool detects that HD.ISOLATED property is set to true.