Step 11: Creating Vitis Application to Load Partial Bitstreams

Isolation Design Flow + Dynamic Function eXchange Example Application Note (XAPP1361)

Document ID
XAPP1361
Release Date
2024-05-23
Revision
1.2 English

For this particular example design, partial bitstreams are placed into PS-DDR memory and loaded into the device using a baremetal application, running on the Cortex-A53. This application takes inputs from the user through a UART to select the RM to load. The application uses the xilfpga library to load the partial bitstreams through the PCAP. More information on the xilfpga library can be found in the Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137).

Perform the following steps to create the software application.

  1. In Vivado, select File > Export > Export Hardware.
  2. Click Next in the Export hardware platform window.
  3. Leave the output set to Pre-synthesis on the output window, and click Next.
  4. Change the XSA file name to top and the Export to as a location of the project directory. Click Next and then select Finish to build a design image for the Vitis integrated design environment. This creates the top.xsa file under the project_idf_dfx_zcu102 directory.
  5. Select Tools > Launch Vitis IDE. The Eclipse launcher dialog box appears in Vivado.
  6. Ensure the workspace maps to the current project directory (project_idf_dfx_zcu102) in the Eclipse launcher, and then click Launch to open the main Vitis integrated design environment GUI.
  7. Select File > New > Application Project in the Vitis IDE.
  8. Click Next on the welcome screen.
  9. Select the Create a new platform from hardware (XSA) tab, and browse to select top.xsa to import the file that was exported from Vivado.
  10. Keep the platform name as top, select Generate boot components, and select psu_cortexa53_0.

  11. Click Next.
  12. Name the project dfx_demo in the Application Project window, and select psu_cortexa53_0 as the target processor. Click Next.

  13. Keep default values for Domain, and click Next.

  14. Select Empty Application(C), and click Finish.
  15. Expand dfx_demo in the Project Explorer window. Right-click src and select Import Sources. Browse to the sources/dfx_demo/src directory, and click Open. Finally, check all .c and .h sources in that folder, and click Finish.
    Important: If the actual bitstream file size does not match with the size of bit file in dfx_demo.h, then loading the partial bitlstream on hardware might fail. Check the size of partial bitstream files (.bin) and update the new bitstream file size in dfx_demo.h. Update the address range in bif file accordingly.


  16. The application uses the xilfpga library to load the partial bitstreams via PCAP. More information on the xilfpga library can be found in the Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137). You must enable the xilfpga and dependent libraries in the BSP settings. Select dfx_demo.prj and click Navigate to BSP settings.

  17. Select Board Support Package under standalone_psu_cortexa53_0 and then click Modify BSP Settings.

  18. Select xilfpga, xilsecure, and xilskey from the supported libraries list.
  19. Select Overview > standalone, then select xilfpga to open configuration for the library. Change the secure_mode value to false.

  20. Click OK.
  21. Open the dfx_demo_system settings and disable Generate SD card image.

  22. Build the dfx_demo project, and generate dfx_demo.elf. To build the project, select the project from the Explorer drop-down list, and click Project > Build Project.

  23. Create a boot image, which loads partial bitstreams into the PS-DDR and initializes PL with the Config1 full bitstream. Click Xilinx > Create Boot Image > Zynq and Zynq Ultrascale. Select Import from existing BIF file option, browse to the directory where you placed the application note files, and then select and open dfx_demo.bif.
    Important: Check the load address of the partial bitstreams. The address range should be more than the actual bitstream file size.