The following table describes S_AXIS_STS_SB_RX interface ports:
| Signal | I/O | Description |
|---|---|---|
| intf0_ctrl_sb_rx_tdata | I |
Sideband signal information from transceiver block bit 0: rx_change_done—Indicates that SDI line rate is successful bit 2: gtrxresetdone bit 3: rx_m bit 8: rx_fabric_rst—SMPTE UHD-SDI RX IP is reset when this bit set to 1. All other bits are not used. |
| intf0_ctrl_sb_rx_tvalid | I | Data valid |
| intf0_ctrl_sb_rx_tready | O | Core ready |