Resets - 2.1 English

UHD-SDI GT LogiCORE IP Product Guide (PG380)

Document ID
PG380
Release Date
2024-06-14
Version
2.1 English

The Rate Detect Module looks for the clock frequency change and generates a reset signal whenever there is asynchronous clock switching due to rate change or any other reason. It also indicates whenever a drift is seen in the recovered clock beyond a threshold value. This module validates the changes number of times before generating the reset or clock drift status signals.

Reset Sequence:

  1. Assert Reset
  2. Wait for resetdone to be asserted
  3. Wait for plllock to be asserted

Reset is now complete.