cmp_gt_ctrl
input ports are control inputs used in the SMPTE UHD-SDI GT IP and/or
transceiver including GT COMMON. See the respective transceiver user guide for more
information.
Bit | Description |
---|---|
0 | GT COMMON QPLL0 reset |
1 | GT COMMON QPLL0 Power down |
2 | GT COMMON QPLL1 reset |
3 | GT COMMON QPLL1 Power down |
6:4 | GT COMMON QPLL0 REFCLKSEL |
7 | GT COMMON QPLL0 REFCLKSEL valid |
10:8 | GT COMMON QPLL1 REFCLKSEL |
11 | GT COMMON QPLL1 REFCLKSEL valid |
12 | Link 0 CPLL reset. Provide Link 0 CPLL Power down input along with CPLL reset input to reset CPLL properly. |
13 | Link 0 CPLL Power down |
14 | txclk_ready. Connect the signal that indicates that TX reference clock is stable for Link 0. |
15 | rxclk_ready. Connect the signal that indicates that RX reference clock is stable for Link 0. |
18:16 |
CPLLREFCLKSEL port selection for Link 0. Input to dynamically select the input reference clock to the Channel PLL. 000: Reserved 001: GTREFCLK0 selected 010: GTREFCLK1 selected 011: GTNORTHREFCLK0 selected 100: GTNORTHREFCLK1 selected 101: GTSOUTHREFCLK0 selected 110: GTSOUTHREFCLK1 selected 111: GTGREFCLK selected. |
19 | To enable CPLLREFCLKSEL input for Link 0. For Link 0, when this bit is set to 1, only bits[18:16] of cmp_gt_ctrl will select the reference clock value for CPLL. The selected value is fed to the CPLLREFCLKSEL input of the GT Transceiver. If the bit is unset, the reference clock selection will be automatically handled by design. |
22:20 | Link 0 GT LOOPBACK |
23 | Unused |
24 | Link 1 CPLL reset. Provide Link 1 CPLL Power down input along with CPLL reset input to reset CPLL properly. |
25 | Link 1 CPLL Power down |
26 | txclk_ready. Connect the signal that indicates that TX reference clock is stable for Link 1. |
27 | rxclk_ready. Connect the signal that indicates that RX reference clock is stable for Link 1. |
30:28 |
CPLLREFCLKSEL port selection for Link 1. Input to dynamically select the input reference clock to the Channel PLL. 000: Reserved 001: GTREFCLK0 selected 010: GTREFCLK1 selected 011: GTNORTHREFCLK0 selected 100: GTNORTHREFCLK1 selected 101: GTSOUTHREFCLK0 selected 110: GTSOUTHREFCLK1 selected 111: GTGREFCLK selected. |
31 | To enable CPLLREFCLKSEL input for Link 1. For Link 1, when this bit is set to 1, then only bits[30:28] of cmp_gt_ctrl are used to select the reference clock value for CPLL. The selected value is fed to the CPLLREFCLKSEL input of the GT Transceiver. If the bit is unset, the reference clock selection will be automatically handled by design. |
34:32 | Link 1 GT LOOPBACK |
35 | Unused |
36 | Link 2 CPLL reset. Provide Link 2 CPLL Power down input along with CPLL reset input to reset CPLL properly. |
37 | Link 2 CPLL Power down |
38 | txclk_ready. Connect the signal that indicates that TX reference clock is stable for Link 2. |
39 | rxclk_ready. Connect the signal that indicates that RX reference clock is stable for Link 2. |
42:40 |
CPLLREFCLKSEL port selection for Link 2. Input to dynamically select the input reference clock to the Channel PLL. 000: Reserved 001: GTREFCLK0 selected 010: GTREFCLK1 selected 011: GTNORTHREFCLK0 selected 100: GTNORTHREFCLK1 selected 101: GTSOUTHREFCLK0 selected 110: GTSOUTHREFCLK1 selected 111: GTGREFCLK selected. |
43 | To enable CPLLREFCLKSEL input for Link 2. When this bit is set to 1, then only bits[42:40] of cmp_gt_ctrl will be used to select the reference clock value for CPLL for link 2. The selected value be fed to the CPLLREFCLKSEL input of the GT Transceiver. If the bit is unset, the reference clock selection will be automatically handled by design. |
46:44 | Link 2 GT LOOPBACK |
47 | Unused |
48 | Link 3 CPLL reset |
49 | Link 3 CPLL reset. Provide Link 3 CPLL Power down input along with CPLL reset input to reset CPLL properly. |
50 | txclk_ready. Connect the signal that indicates that TX reference clock is stable for Link 3. |
51 | rxclk_ready. Connect the signal that indicates that RX reference clock is stable for Link 3. |
54:52 |
CPLLREFCLKSEL port selection for Link 3. Input to dynamically select the input reference clock to the Channel PLL. 000: Reserved 001: GTREFCLK0 selected 010: GTREFCLK1 selected 011: GTNORTHREFCLK0 selected 100: GTNORTHREFCLK1 selected 101: GTSOUTHREFCLK0 selected 110: GTSOUTHREFCLK1 selected 111: GTGREFCLK selected. |
55 | To enable CPLLREFCLKSEL input for Link 3. When this bit is set to 1, then only bits[54:52] of cmp_gt_ctrl will be used to select the reference clock value for CPLL Link3. The selected value be fed to the CPLLREFCLKSEL input of the GT Transceiver. If the bit is unset, the reference clock selection will be automatically handled by design. |
58:56 | Link 3 GT LOOPBACK |
63:59 | Unused |