Required Constraints
This section defines the additional constraint requirements for the core. Constraints are provided with an Xilinx Design Constraints (XDC) file. The XDC file is provided with the HDL example design to give a starting point for constraints in your design.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
drpclk_in should be specified using the following
command:create_clock -name drp_clk -period 10.000 [get_ports drpclk_in]drpclk_in that is supplied to DRP
control logic and connected to DRPCLK of GT CHANNEL primitive.Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
The UHD-SDI GT core does not have the ability to
constrain the transceiver. Constraining the txp, txn,
rxp, and rxn ports of GTHE4_CHANNEL/GTYE4_CHANNEL is
sufficient for transceiver placement.
I/O Standard and Placement
The UHD-SDI GT core generates clock constraints and necessary false path constraints. But it does not constrain GT locations and reference clock locations. See the respective board user guide or board schematics for LOC and add the constraints to the top level XDC file.