Core Specifics |
Supported Device Family
1
|
AMD Kintex™
UltraScale+™
,
AMD Virtex™
UltraScale+™
(GTHE4 & GTYE4),
AMD Zynq™
UltraScale+™ MPSoC (GTHE4 & GTYE4),
AMD Zynq™
UltraScale+™ RFSoC
AMD
Artix™
AMD UltraScale+™
(GTHE4 & GTYE4) |
Supported User Interfaces |
Not Applicable |
Resources |
Performance and Resource Use web page
|
Provided with
Core
|
Design Files |
RTL |
Example Design |
Verilog |
Test Bench |
N/A |
Constraints File |
Xilinx Design Constraints (XDC) |
Simulation Model |
N/A |
Supported S/W Driver |
Not Provided |
Tested Design
Flows
2
|
Design Entry |
AMD Vivado™ Design Suite
|
Simulation |
For supported simulators, see the Vivado
Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Record: 70291
|
All Vivado IP Change
Logs |
Master Vivado IP Change
Logs:72775
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release Notes, Installation,
and Licensing (UG973).
- All devices having GTHE4 & GTYE4 transceivers support the UHD-SDI GT
IP.
|