The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter | User Parameter | Default Value |
|---|---|---|
| Core Parameters | ||
| GT Type | C_GT_TYPE | GTHE4 |
| Data Flow | C_DATA_FLOW | Duplex |
| LINE RATE | C_LINE_RATE | 12G-SDI |
| SDI link(s) | C_SDI_LINKS | 1 |
| GT COMMON Shared Logic | SupportLevel | 1 (include GT COMMON in the core) |
| QPLL0 Ref Clock Selection | C_QPLL0_Refclk_Sel | GTREFCLK0 |
| QPLL1 Ref Clock Selection | C_QPLL1_Refclk_Sel | GTREFCLK1 |
| CPLL Ref Clock Selection (Integer) | C_CPLL0_Refclk_Sel | GTREFCLK0 |
| CPLL Ref Clock Selection (Fractional) | C_CPLL1_Refclk_Sel | GTREFCLK0 |
| DRP Clock Frequency | C_DRP_CLK_FREQ | 100.0 |
| LINE_RATE | C_LINE_RATE | 12G-SDI |
| Enable_PICXO_Ports | C_Enable_PICXO_Ports | False |
| MODE | C_SDI_MODE | PICXO |
| SDI Link 0 | ||
| Link 0 TX PLL1 Type | C_Tx_PLL_Selection_INTF_0 | No default value is assigned. User selection is mandatory. |
| Link 0 RX PLL1 Type | C_Rx_PLL_Selection_INTF_0 | |
| Link 0 TX PLL2 Type | C_Tx_PLL2_Selection_INTF_0 | |
| Link 0 RX PLL2 Type | C_Rx_PLL2_Selection_INTF_0 | |
| SDI Link 1 | ||
| Link 1 TX PLL1 Type | C_Tx_PLL_Selection_INTF_1 | No default value is assigned. User selection is mandatory |
| Link 1 RX PLL1 Type | C_Rx_PLL_Selection_INTF_1 | |
| Link 1 TX PLL2 Type | C_Tx_PLL2_Selection_INTF_1 | |
| Link 1 RX PLL2 Type | C_Rx_PLL2_Selection_INTF_1 | No default value is assigned. User selection is mandatory |
| SDI Link 2 | ||
| Link 2 TX PLL1 Type | C_Tx_PLL_Selection_INTF_2 | No default value is assigned. User selection is mandatory |
| Link 2 RX PLL1 Type | C_Rx_PLL_Selection_INTF_2 | |
| Link 2 TX PLL2 Type | C_Tx_PLL2_Selection_INTF_2 | |
| Link 2 RX PLL2 Type | C_Rx_PLL2_Selection_INTF_2 | |
| SDI Link 3 | ||
| Link 3 TX PLL1 Type | C_Tx_PLL_Selection_INTF_3 | No default value is assigned. User selection is mandatory |
| Link 3 RX PLL1 Type | C_Rx_PLL_Selection_INTF_3 | |
| Link 3 TX PLL2 Type | C_Tx_PLL2_Selection_INTF_3 | |
| Link 3 RX PLL2 Type | C_Rx_PLL2_Selection_INTF_3 | |