Clock Frequencies and Clock Enable Requirements - 2.1 English

The frequency of the rxusrclk and txusrclk depend on the SDI mode and the width of the rxdata and txdata ports of the GTH/GTY transceiver. This relationship is fixed by the architecture of the GTH/GTY transceiver. The RX and the TX both use clock enables to throttle the data stream transfer data rate because, in some cases, the data rate on the data streams is less than the frequency of the clock. Table 1 shows the relationships between SDI mode, number of active data streams, rxdata/txdata port widths, rxoutclk/txoutclk frequencies, and clock enable cadences. The clock enable cadences are given in number of clocks between assertions of the clock enable over two data word cycles where 1/1 means that the clock enable is asserted every clock cycle, 2/2 indicates assertion every other clock cycle (50% duty cycle), 4/4 indicates assertion every fourth clock cycle (25% duty cycle), and 5/6 indicates that the clock enable alternates between assertion every 5 or 6 clock cycles, to average once every 5.5 clock cycles (one instance of 5 clock cycles between High pulses on the clock enabled followed by one instance of six clock cycles between High pulses on the clock enable, with this pattern repeating).