The GTH/GTY transmitter clocking is handled by the Transmitter User Clocking
Network Helper block when enabled during GT IP generation from the AMD UltraScale™
FPGAs Transceiver Wizard. The txusrclk and txusrclk2
output is driven by a BUFG_GT within the helper block and its frequency is exactly equal
to the word rate of the data that must enter the txdata port of the GTH/GTY transmitter. The txusrclk and txusrclk2 are generated in
the GTH/GTY transmitter by dividing the serial clock from the PLL down to the word rate.
See the
UltraScale
FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182) for more details on
Transmitter User Clocking Network Helper block.