One additional clock is required for SDI applications. This is a free-running, fixed-frequency clock that is used as the clock for the dynamic reconfiguration port (DRP) of the GTH/GTY transceiver. This same clock is also usually supplied to the control module in the SDI wrapper where it is used for timing purposes. The valid frequency range for this clock is stated in the UltraScale FPGAs Transceiver Wizard and normally ranges from 3.125 to 200 MHz. The frequency of this clock does not require any specific relationship relative to other clocks or data rates of the SDI application. This clock must not change frequencies when the SDI mode changes. It must remain running at the same nominal frequency at all times. It also must never stop while the SDI application is active. This clock can be used for all SD interfaces in the device.