During write per-bit deskew step, a known pattern is written and read back. First, DQS delay taps are incremented until valid data is read back on all the DQ bits associated with a DQS. Next, delay taps of DQ bits are incremented until invalid data is read back on every DQ bit thereby edge aligning all DQ bits to its associated DQS.
For DBI deskew, enable write DBI and increment DQS delay taps until valid data is read back on all DQ bits. Next, delay DBI until invalid data is read back on all DQ bits.