Project-Based Simulation - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

This method can be used to simulate the example design using the Vivado Design Suite (IDE). Memory IP delivers IEEE encrypted memory models for DDR4.

The Vivado simulator, Questa Advanced Simulator, IES, and VCS tools are used for DDR4 IP verification at each software release. The Vivado simulation tool is used for DDR4 IP verification from 2021.2 Vivado software release. The following subsections describe steps to run a project-based simulation using each supported simulator tool.