This register stores the (corrected) failing data (Bits[63:32]) of the first occurrence of an access with a correctable error. When the CE_STATUS bit in the ECC Status register is cleared, this register is re-enabled to store the data of the next correctable error. Storing of the failing data is enabled after reset.
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
31:0 | CE_FFD[63:32] | R | 0 | Data (Bits[63:32]) of the first occurrence of a correctable error. |