The following table lists the AXI4 slave
interface specific signal. ui_clk and
ui_clk_sync_rst to the interface is provided from the Memory
Controller. AXI interface is synchronous to ui_clk.
| Name | Width | I/O | Active State | Description |
|---|---|---|---|---|
| ui_clk | 1 | O | Output clock from the core to the interface. | |
| ui_clk_sync_rst | 1 | O | High | Output reset from the core to the interface. |
| aresetn | 1 | I | Low | Input reset to the AXI Shim and it should be in synchronous with Versal adaptive SoC logic clock. |
| s_axi_awid | C_S_AXI_ID_WIDTH | I | Write address ID | |
| s_axi_awaddr | C_S_AXI_ADDR_WIDTH | I | Write address | |
| s_axi_awlen | 8 | I | Burst length. The burst length gives the exact number of transfers in a burst. | |
| s_axi_awsize | 3 | I | Burst size. This signal indicates the size of each transfer in the burst. | |
| s_axi_awburst | 2 | I | Burst type. Only INCR/WRAP supported. | |
| s_axi_awlock | 1 | I | Lock type (This is not used in the current implementation.) Note: When an unsupported value is selected, awburst
defaults to an INCR burst type.
|
|
| s_axi_awcache | 4 | I | Cache type (This is not used in the current implementation.) | |
| s_axi_awprot | 3 | I | Protection type (This is not used in the current implementation.) | |
| s_axi_awqos | 4 | I | Quality of service (This is not used in the current implementation.) | |
| s_axi_awvalid | 1 | I | High | Write address valid. This signal indicates that valid write address and control information are available. |
| s_axi_awready | 1 | O | High | Write address ready. This signal indicates that the slave is ready to accept an address and associated control signals. |
| s_axi_wdata | C_S_AXI_DATA_WIDTH | I | Write data | |
| s_axi_wstrb | C_S_AXI_DATA_WIDTH/8 | I | Write strobes | |
| s_axi_wlast | 1 | I | High | Write last. This signal indicates the last transfer in a write burst. |
| s_axi_wvalid | 1 | I | High | Write valid. This signal indicates that write data and strobe are available. |
| s_axi_wready | 1 | O | High | Write ready |
| s_axi_bid | C_S_AXI_ID_WIDTH | O | Response ID. The identification tag of the write response. | |
| s_axi_bresp | 2 | O | Write response. This signal indicates the status of the write response. | |
| s_axi_bvalid | 1 | O | High | Write response valid |
| s_axi_bready | 1 | I | High | Response ready |
| s_axi_arid | C_S_AXI_ID_WIDTH | I | Read address ID | |
| s_axi_araddr | C_S_AXI_ADDR_WIDTH | I | Read address | |
| s_axi_arlen | 8 | I | Read burst length | |
| s_axi_arsize | 3 | I | Read burst size | |
| s_axi_arburst | 2 | I | Read burst type. Only INCR/WRAP supported. | |
| s_axi_arlock | 1 | I | Lock type (This is not used in the current implementation.) Note: When an unsupported value is selected, arburst
defaults to an INCR burst type.
|
|
| s_axi_arcache | 4 | I | Cache type (This is not used in the current implementation.) | |
| s_axi_arprot | 3 | I | Protection type (This is not used in the current implementation.) | |
| s_axi_arqos | 4 | I | Quality of service (This is not used in the current implementation.) | |
| s_axi_arvalid | 1 | I | High | Read address valid |
| s_axi_arready | 1 | O | High | Read address ready |
| s_axi_rid | C_S_AXI_ID_WIDTH | O | Read ID tag | |
| s_axi_rdata | C_S_AXI_DATA_WIDTH | O | Read data | |
| s_axi_rresp | 2 | O | Read response | |
| s_axi_rlast | 1 | O | Read last | |
| s_axi_rvalid | 1 | O | Read valid | |
| s_axi_rready | 1 | I | Read ready | |
| dbg_clk | 1 | O | Debug Clock. Do not connect any signals to dbg_clk and keep the port open during instantiation. |