Bus Usage - 1.0 English

Versal Adaptive SoC Soft DDR4 SDRAM Memory Controller LogiCORE IP Product Guide (PG353)

Document ID
PG353
Release Date
2023-10-18
Version
1.0 English

The bus usage is calculated at the User Interface taking total number of Reads and Writes into consideration and the following equation is used:

                ((rd_command_cnt + wr_command_cnt) × (BURST_LEN / 2) × 100)
bw_cumulative = -----------------------------------------------------------
                        ((wr_rd_complete – calib_done) / tCK)
  • BURST_LEN equals 8 for DDR4. BURST_LEN is divided by 2 in the BW formula to give the number tCK of data activity on the DDR bus for each read and write.
  • rd_command_cnt and wr_command_cnt are the total number of read and write commands accepted at the User Interface between calib_done and end_of_stimulus.
  • wr_rd_complete is the time when all the commands are done.
  • calib_done is the time when the calibration is done.