This register stores the decoded address (Bits[55:32]) of the first
occurrence of an access with an uncorrectable error. The address format is defined
in the Error Address section. In addition, the upper byte of this register stores
the ecc_multiple signal. When the UE_STATUS bit in the ECC Status
register is cleared, this register is re-enabled to store the address of the next
uncorrectable error. Storing of the failing address is enabled after reset.
| Bits | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| 31:24 | UE_FFA[63:56] | R | 0 | ecc_multiple[7:0]. Indicates which bursts of the BL8 transaction associated with the logged address had an uncorrectable error. Bit[24] corresponds to the first burst of the BL8 transfer. |
| 23:0 | UE_FFA[55:32] | R | 0 | Address (Bits[55:32]) of the first occurrence of a correctable error. |