The following table shows the command and address signals for a PHY only option.
| Signal | I/O | Description |
|---|---|---|
| mc_ACT_n[7:0] | I | DRAM ACT_n command signal for four DRAM clock cycles. Bits[1:0]
correspond to the first DRAM clock cycle, Bits[3:2] to the second,
Bits[5:4] to the third, and Bits[8:7] to the fourth. For center alignment to the DRAM clock with 1N timing, both bits of a given bit pair should be asserted to the same value. See timing diagrams for examples. All of the command/address ports in this table follow the same eight bits per DRAM pin format. Active-Low. |
| mc_ADR[ADDR_WIDTH × 8 – 1:0] | I | DRAM address. Eight bits in the PHY interface for each address bit on
the DRAM bus. Bits[7:0] corresponds to DRAM address Bit[0] on four DRAM clock cycles. Bits[15:8] corresponds to DRAM address Bit[1] on four DRAM clock cycles, etc. See the timing diagrams for examples. All of the multi-bit DRAM signals in this table follow the same format of 1-byte of the PHY interface port corresponding to four commands for one DRAM pin. Mixed active-Low and High depending on which type of DRAM command is being issued, but follows the DRAM pin active-High/Low behavior. The function of each byte of the mc_ADR port depends on whether the memory type is DDR4 and the particular DRAM command that is being issued. These functions match the DRAM address pin functions. For example, with DDR4 memory and the mc_ACT_n port bits asserted High, mc_ADR[135:112] have the function of RAS_n, CAS_n, and WE_n pins. |
| mc_BA[BANK_WIDTH × 8 – 1:0] | I | DRAM bank address. Eight bits for each DRAM bank address. |
| mc_BG[BANK_GROUP_WIDTH × 8 – 1:0] | I | DRAM bank group address. Eight bits for each DRAM pin. |
| mc_C[LR_WIDTH × 8 – 1:0] | I | DDR4 DRAM Chip ID pin. Valid for 3DS RDIMMs only. LR_WIDTH is log2 (StackHeight) where StackHeight (S_HEIGHT) is 2 or 4. |
| mc_CKE[CKE_WIDTH × 8 – 1:0] | I | DRAM CKE. Eight bits for each DRAM pin. |
| mc_CS_n[CS_WIDTH × 8 – 1:0] | I | DRAM CS_n. Eight bits for each DRAM pin. Active-Low. |
| mc_ODT[ODT_WIDTH × 8 – 1:0] | I | DRAM ODT. Eight bits for each DRAM pin. Active-High. |
| mc_PAR[7:0] | I | DRAM address parity. Eight bits for one DRAM parity pin. Note: This signal
is valid for RDIMMs/LRDIMMs only.
|
The following figure shows the functional relationship between the PHY
command/address input signals and a DDR4
command/address bus. The diagram shows an Activate command on system clock cycle N in
the slot1 position. The mc_ACT_n[3:2] and mc_CS_n[3:2]
are both asserted Low in cycle N, and all the other bits in cycle N are asserted High,
generating an Activate in the slot1 position roughly two system clocks later and
NOP/DESELECT commands on the other command slots.
On cycle N + 3, mc_CS_n and the mc_ADR bits corresponding to CAS/A15 are set to 0xFC. This asserts mc_ADR[121:120] and mc_CS_n[1:0] Low,
and all other bits in cycle N + 3 High, generating a read command on slot0 and
NOP/DESELECT commands on the other command slots two system clocks later. With the
Activate and read command separated by three system clock cycles and taking into account
the command slot position of both commands within their system clock cycle, expect the
separation on the DDR4 bus to be 11 DRAM
clocks, as shown in the DDR bus portion of the following figure.
The following figure shows an example of using all four command slots in a single system clock. This example shows three commands to rank0, and one to rank1, in cycle N. BG and BA address pins are included in the diagram to spread the commands over different banks to not violate DRAM protocol. The following table lists the command in each command slot.
| Command Slot | 0 | 1 | 2 | 3 |
|---|---|---|---|---|
| DRAM Command | Read | Activate | Precharge | Refresh |
| Bank Group | 0 | 1 | 2 | 0 |
| Bank | 0 | 3 | 1 | 0 |
| Rank | 0 | 0 | 0 | 1 |
To understand how DRAM commands to different command slots are packed together,
the following detailed example shows how to convert DRAM commands at the PHY interface
to commands on the DRAM command/address bus. To convert PHY interface commands to DRAM
commands, write out the PHY signal for one system clock in binary and reverse the bit
order of each byte. You can also drop every other bit after the reversal because the bit
pairs are required to have the same value. In the subsequent example, the
mc_BA[15:0] signal has a cycle N value of 0x0C3C:
| Hex | 0x0C3C |
| Binary | 16'b0000_1100_0011_1100 |
| Reverse bits in each byte | 16'b0011_0000_0011_1100 |
Take the upper eight bits for DRAM BA[1] and the lower eight
bits for DRAM BA[0] and the expected pattern on the DRAM bus is:
| BA[1] | 00 | 11 | 00 | 00 |
| 0 | 1 | 0 | 0 | |
| Low | High | Low | Low | |
| BA[0] | 00 | 11 | 11 | 00 |
| 0 | 1 | 1 | 0 | |
| Low | High | High | Low |
This matches the DRAM BA[1:0] signal values of 0, 3, 1, and
0 shown in Figure 2.