- Supports Memory Device Types: Components, SODIMMs, UDIMMs, RDIMMs,
LRDIMMs
- Supports these data widths: 8, 16, 24, 32, 40, 48, 56, 64, and 72
- Maximum component limit is nine and this restriction is valid for components only and not for DIMMs
- Density support
- Supports Row Address Widths: 15, 16, 17, and 18
- Supports Bank Address Width: 2
- Supports Bank Group Widths: 1 and 2
- Support densities up to 64 GB for components, 256 GB for LRDIMMs, 256 GB for RDIMMs, 128 GB for SODIMMs, and 32 GB for UDIMMs
-
AXI4 Slave Interface
- Supports AXI Data Widths: 64, 128, 256, and 512
- Supports ID Widths: 1 to 6
- Optional AXI Narrow Burst support
Note: The x4-based component interfaces do not support AXI4, while x4-based RDIMM and LRDIMM does support AXI4. - x4, x8, and x16 components are supported
- Single and dual slot support for DDR4 RDIMMs, SODIMMs, LRDIMMs, and UDIMMs
- Supports number of ranks: 1, 2, and 4
- Supports Stack Heights: 1, 2, and 4
- 8-word burst support
- ODT support
- 3DS RDIMM and LRDIMM support
- 3DS component support
- Source code delivery in Verilog
- 4:1 memory to Versal adaptive SoC logic interface clock ratio
- Open, closed, and transaction based pre-charge controller policy
- Interface calibration and training information available through the AMD Vivado™ hardware manager
- Optional Error Correcting Code (ECC) support for non-AXI4 72-bit, 40-bit, and 24-bit interfaces
- 2T timing for Address/Command bus is supported
- Optional support for User Refresh, User ZQCS, Auto Precharge, DDR4_AUTO_AP_COL_A3, DDR4_isCKEShared, and CA MIRROR
- Supports Write DBI: DM_NO_DBI, NO_DM_DBI, NONE
- Supports Read DBI options: TRUE and FALSE
- Supports DDR4 ordering: Strict and Normal