Reset Sequence - 1.0 English

The sys_rst signal resets the entire memory interface design which includes general interconnect (fabric) logic, RIU interface logic, MicroBlaze™ , and calibration logic. The sys_rst input signal is synchronized internally to create the ui_clk_sync_rst signal. The ui_clk_sync_rst reset signal is synchronously asserted and synchronously deasserted.

The following figure shows the ui_clk_sync_rst signal (fabric reset) is synchronously asserted with a few clock delays after the sys_rst signal is asserted. When the ui_clk_sync_rst signal is asserted, there are a few clocks before the clocks are shut off.

The following are the reset sequencing steps:

1. Reset to design is initiated after the ui_clk_sync_rst signal goes High.
2. The init_calib_complete signal goes Low when the ui_clk_sync_rst signal is High.
3. Reset to design is deactivated after the ui_clk_sync_rst signal is Low.
4. After the ui_clk_sync_rst signal is deactivated, the init_calib_complete signal is asserted after calibration is completed.