Simple SRAM Model - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

Document ID
PG267
Release Date
2024-06-07
Version
1.1 English

The AXI slave VIP has a simple memory mode. It is an associative array of SystemVerilog as shown in the following figure. The write transaction can write to the memory model and the read transaction can read data from the memory (also called front door access to differ from the backdoor access APIs). These two features are implemented in the AXI slave VIP and AXI pass-through VIP in runtime slave mode. At the same time, the memory model has backdoor APIs for you to access memory directly, which are backdoor_memory_write and backdoor_memory_read. The backdoor_memory_write writes data to memory and backdoor_memory_read reads data from memory. For usage of memory model APIs, see the AXI VIP API Documentation.

Figure 1. Memory Model
Important: This memory has no support for built-in system tasks such as readmemh. Use the backdoor_memory_write to write all of the file information into the memory. Reset has no effect on memory content.