IP Facts - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

Document ID

PG267

Release Date

2023-10-18

Version

1.1 English

AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family¹	AMD UltraScale+™ , AMD UltraScale™ AMD Zynq™ 7000 SoC 7 series FPGAs
Supported User Interfaces	AXI4, AXI4-Lite, AXI3
Resources	N/A
Provided with Core
Design Files	SystemVerilog
Example Design	SystemVerilog
Test Bench	N/A
Constraints File	N/A
Simulation Model	Unencrypted SystemVerilog
Supported S/W Driver	N/A
Tested Design Flows^2, ³
Design Entry	AMD Vivado™ Design Suite
Simulation⁴	For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: 68234
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Support web page
For a complete list of supported devices, see the AMD Vivado™ IP catalog. For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). This IP does not deliver VIP for Zynq PS. It only delivers the VIP core for AXI3, AXI4, and AXI4-Lite interfaces. To take advantage of the full features of this IP, it requires simulators supporting advanced simulation capabilities. The AXI VIP can only act as a protocol checker when contained within a VHDL hierarchy. To use the virtual part of the AXI Verification IP, it must be in a Verilog hierarchy. Do not import two different revisions/versions of the `axi_vip` packages. This causes elaboration failures. All AXI VIP and parents to the AXI VIP must be upgraded to the latest version.