AXI Protocol Checks and Descriptions

The following table lists the AXI protocol checks and descriptions that are essentially the same as the assertions found in the AXI Protocol Checker LogiCORE IP Product Guide (PG101).

Table 1. AXI Protocol Checks and Descriptions
Name of Protocol Check	Protocol Support	Description
AXI_ERRM_AWADDR_BOUNDARY	AXI4/AXI3	A write burst cannot cross a 4 KB boundary.
AXI_ERRM_AWADDR_WRAP_ALIGN	AXI4/AXI3	A write transaction with burst type WRAP has an aligned address.
AXI_ERRM_AWBURST	AXI4/AXI3	A value of 2’b11 on AWBURST is not permitted when AWVALID is High.
AXI_ERRM_AWLEN_LOCK	AXI4/AXI3	Exclusive access transactions cannot have a length greater than 16 beats.
AXI_ERRM_AWCACHE	AXI4/AXI3	If not cacheable (AWCACHE[1] == 1'b0), AWCACHE = 2'b00.
AXI_ERRM_AWLEN_FIXED	AXI4/AXI3	Transactions of burst type FIXED cannot have a length greater than 16 beats.
AXI_ERRM_AWLEN_WRAP	AXI4/AXI3	A write transaction with burst type WRAP has a length of 2, 4, 8, or 16.
AXI_ERRM_AWSIZE	AXI4/AXI3	The size of a write transfer does not exceed the width of the data interface.
AXI_ERRM_AWVALID_RESET	AXI4/AXI3/Lite	AWVALID is Low for the first cycle after ARESETn goes High.
AXI_ERRM_AWADDR_STABLE	AXI4/AXI3/Lite	Handshake Checks AWADDR must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWBURST_STABLE	AXI4/AXI3	Handshake Checks AWBURST must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWCACHE_STABLE	AXI4/AXI3	Handshake Checks AWCACHE must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWID_STABLE	AXI4/AXI3	Handshake Checks AWID must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWLEN_STABLE	AXI4/AXI3	Handshake Checks AWLEN must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWLOCK_STABLE	AXI4/AXI3	Handshake Checks AWLOCK must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWPROT_STABLE	AXI4/AXI3/Lite	Handshake Checks AWPROT must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWSIZE_STABLE	AXI4/AXI3	Handshake Checks AWSIZE must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWQOS_STABLE	AXI4/AXI3	Handshake Checks AWQOS must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_AWREGION_STABLE	AXI4	Handshake Checks AWREGION must remain stable when ARVALID is asserted and AWREADY Low.
AXI_ERRM_AWVALID_STABLE	AXI4/AXI3/Lite	Handshake Checks Once AWVALID is asserted, it must remain asserted until AWREADY is High.
AXI_RECS_AWREADY_MAX_WAIT	AXI4/AXI3/Lite	Recommended that AWREADY is asserted within MAXWAITS cycles of AWVALID being asserted.
AXI_ERRM_WDATA_NUM	AXI4/AXI3	The number of write data items matches AWLEN for the corresponding address. This is triggered when any of the following occurs: Write data arrives and WLAST is set, and the WDATA count is not equal to AWLEN Write data arrives and WLAST is not set, and the WDATA count is equal to AWLEN ADDR arrives, WLAST is already received, and the WDATA count is not equal to AWLEN
AXI_ERRM_WSTRB	AXI4/AXI3/Lite	Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size, and Beat Number.
AXI_ERRM_WVALID_RESET	AXI4/AXI3/Lite	WVALID is Low for the first cycle after ARESETn goes High.
AXI_ERRM_WDATA_STABLE	AXI4/AXI3/Lite	Handshake Checks WDATA must remain stable when WVALID is asserted and WREADY Low.
AXI_ERRM_WLAST_STABLE	AXI4/AXI3	Handshake Checks WLAST must remain stable when WVALID is asserted and WREADY Low.
AXI_ERRM_WSTRB_STABLE	AXI4/AXI3/Lite	Handshake Checks WSTRB must remain stable when WVALID is asserted and WREADY Low.
AXI_ERRM_WVALID_STABLE	AXI4/AXI3/Lite	Handshake Checks Once WVALID is asserted, it must remain asserted until WREADY is High.
AXI_RECS_WREADY_MAX_WAIT	AXI4/AXI3/Lite	Recommended that WREADY is asserted within MAXWAITS cycles of WVALID being asserted.
AXI_ERRS_BRESP_WLAST	AXI4/AXI3	A slave must not take BVALID High until after the last write data is handshake is complete.
AXI_ERRS_BRESP_EXOKAY	AXI4/AXI3	An EXOKAY write response can only be given to an exclusive write access.
AXI_ERRS_BVALID_RESET	AXI4/AXI3/Lite	BVALID is Low for the first cycle after ARESETn goes High.
AXI_ERRS_BRESP_AW	AXI4/AXI3/Lite	A slave must not take BVALID High until after the write address is handshake is complete.
AXI_ERRS_BID_STABLE	AXI4/AXI3	Handshake Checks BID must remain stable when BVALID is asserted and BREADY Low.
AXI_ERRS_BRESP_STABLE	AXI4/AXI3/Lite	Checks BRESP must remain stable when BVALID is asserted and BREADY Low.
AXI_ERRS_BVALID_STABLE	AXI4/AXI3/Lite	Once BVALID is asserted, it must remain asserted until BREADY is High.
AXI_RECM_BREADY_MAX_WAIT	AXI4/AXI3/Lite	Recommended that BREADY is asserted within MAXWAITS cycles of BVALID being asserted.
AXI_ERRM_ARADDR_BOUNDARY	AXI4/AXI3	A read burst cannot cross a 4 KB boundary.
AXI_ERRM_ARADDR_WRAP_ALIGN	AXI4/AXI3	A read transaction with a burst type of WRAP must have an aligned address.
AXI_ERRM_ARBURST	AXI4/AXI3	A value of 2'b11 on ARBURST is not permitted when ARVALID is High.
AXI_ERRM_ARLEN_LOCK	AXI4/AXI3	Exclusive access transactions cannot have a length greater than 16 beats.
AXI_ERRM_ARCACHE	AXI4/AXI3	When ARVALID is High, if ARCACHE[1] is Low, then ARCACHE[3:2] must also be Low.
AXI_ERRM_ARLEN_FIXED	AXI4/AXI3	Transactions of burst type FIXED cannot have a length greater than 16 beats.
AXI_ERRM_ARLEN_WRAP	AXI4/AXI3	A read transaction with burst type of WRAP must have a length of 2, 4, 8, or 16.
AXI_ERRM_ARSIZE	AXI4/AXI3	The size of a read transfer must not exceed the width of the data interface.
AXI_ERRM_ARVALID_RESET	AXI4/AXI3/Lite	ARVALID is Low for the first cycle after ARESETn goes High.
AXI_ERRM_ARADDR_STABLE	AXI4/AXI3/Lite	ARADDR must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARBURST_STABLE	AXI4/AXI3	ARBURST must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARCACHE_STABLE	AXI4/AXI3	ARCACHE must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARID_STABLE	AXI4/AXI3	ARID must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARLEN_STABLE	AXI4/AXI3	ARLEN must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARLOCK_STABLE	AXI4/AXI3	ARLOCK must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARPROT_STABLE	AXI4/AXI3/Lite	ARPROT must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARSIZE_STABLE	AXI4/AXI3	ARSIZE must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARQOS_STABLE	AXI4/AXI3	ARQOS must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARREGION_STABLE	AXI4	ARREGION must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRM_ARVALID_STABLE	AXI4/AXI3/Lite	Once ARVALID is asserted, it must remain asserted until ARREADY is High.
AXI_RECS_ARREADY_MAX_WAIT	AXI4/AXI3/Lite	Recommended that ARREADY is asserted within MAXWAITS cycles of ARVALID being asserted.
AXI_ERRS_RDATA_NUM	AXI4/AXI3	The number of read data items must match the corresponding ARLEN.
AXI_ERRS_RID	AXI4/AXI3	The read data must always follow the address that it relates to. Therefore, a slave can only give read data with an ID to match an outstanding read transaction.
AXI_ERRS_RRESP_EXOKAY	AXI4/AXI3	An EXOKAY read response can only be given to an exclusive read access.
AXI_ERRS_RVALID_RESET	AXI4/AXI3/Lite	RVALID is Low for the first cycle after ARESETn goes High.
AXI_ERRS_RDATA_STABLE	AXI4/AXI3/Lite	RDATA must remain stable when RVALID is asserted and RREADY Low.
AXI_ERRS_RID_STABLE	AXI4/AXI3	RID must remain stable when RVALID is asserted and RREADY Low.
AXI_ERRS_RLAST_STABLE	AXI4/AXI3	RLAST must remain stable when RVALID is asserted and RREADY Low.
AXI_ERRS_RRESP_STABLE	AXI4/AXI3/Lite	RRESP must remain stable when RVALID is asserted and RREADY Low.
AXI_ERRS_RVALID_STABLE	AXI4/AXI3/Lite	Once RVALID is asserted, it must remain asserted until RREADY is High.
AXI_RECM_RREADY_MAX_WAIT	AXI4/AXI3/Lite	Recommended that RREADY is asserted within MAXWAITS cycles of RVALID being asserted.
AXI_ERRM_EXCL_ALIGN	AXI4/AXI3	The address of an exclusive access is aligned to the total number of bytes in the transaction.
AXI_ERRM_EXCL_LEN	AXI4/AXI3	The number of bytes to be transferred in an exclusive access burst is a power of 2, that is, 1, 2, 4, 8, 16, 32, 64, or 128 bytes.
AXI_RECM_EXCL_MATCH	AXI4/AXI3	Recommended that the address, size, and length of an exclusive write with a given ID is the same as the address, size, and length of the preceding exclusive read with the same ID.
AXI_ERRM_EXCL_MAX	AXI4/AXI3	128 is the maximum number of bytes that can be transferred in an exclusive burst.
AXI_RECM_EXCL_PAIR	AXI4/AXI3	Recommended that every exclusive write has an earlier outstanding exclusive read with the same ID.
AXI_ERRM_AWUSER_STABLE	AXI4/AXI3	AWUSER must remain stable when AWVALID is asserted and AWREADY Low.
AXI_ERRM_WUSER_STABLE	AXI4/AXI3	WUSER must remain stable when WVALID is asserted and WREADY Low.
AXI_ERRS_BUSER_STABLE	AXI4/AXI3	BUSER must remain stable when BVALID is asserted and BREADY Low.
AXI_ERRM_ARUSER_STABLE	AXI4/AXI3	ARUSER must remain stable when ARVALID is asserted and ARREADY Low.
AXI_ERRS_RUSER_STABLE	AXI4/AXI3	RUSER must remain stable when RVALID is asserted and RREADY Low.
AXI_AUXM_RCAM_OVERFLOW	AXI4/AXI3/Lite	Read CAM overflow, increase MAXRBURSTS parameter.
AXI_AUXM_RCAM_UNDERFLOW	AXI4/AXI3/Lite	Read CAM Underflow
AXI_AUXM_WCAM_OVERFLOW	AXI4/AXI3/Lite	Write CAM overflow, increase MAXWBURSTS parameter.
AXI_AUXM_WCAM_UNDERFLOW	AXI4/AXI3/Lite	Write CAM Underflow
AXI_AUXM_EXCL_OVERFLOW	AXI4/AXI3	Exclusive access monitor overflow, increase EXMON_WIDTH parameter.
AXI4LITE_ERRS_BRESP_EXOKAY	Lite	A slave must not give an EXOKAY response on an AXI4-Lite interface.
AXI4LITE_ERRS_RRESP_EXOKAY	Lite	A slave must not give an EXOKAY response on an AXI4-Lite interface.
AXI4LITE_AUXM_DATA_WIDTH	Lite	DATA_WIDTH parameter is 32 or 64.

AXI Protocol Checks and Descriptions - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)