This section contains information about using the AXI VIP in a design and test bench environment. The following figure shows a possible design with the AXI VIPs.
The AXI VIP uses similar naming and structures as the Universal Verification Methodology (UVM) for core design. It is coded in SystemVerilog. The AXI VIP is comprised of two parts. One is instanced like other traditional IP (modules in the static/physical world) and the second part is used in the dynamic world in your verification environment. The AXI VIP is an IP, which has a static world connected to the dynamic world with a virtual interface. The virtual interface is the only mechanism that can bridge the dynamic world of objects with the static world of modules and interfaces.