Register Space - 4.1 English

A control register is implemented in the core that allows the driver software to communicate the line-rate information to the core. This allows the core to dynamically adapt to the line-rate changes. Access to this register is through the MDIO interface. The driver software has to initiate a MDIO read/write cycle to read from and write to this register.

IMPORTANT: The driver software must use a PHY address, which is different from the PHY address used to address the onboard PHY. The PHY address for the core can be set through the VHDL generic C_PHYADDR.

Table: Register Space Implementation illustrates the implementation of the register space in the core. This register is within the management module. The management module monitors the MDIO_GEM_O line for a new MDIO cycle. When a new cycle is initiated, and the PHY address matches the PHY address assigned to this core, the module latches the data field of the MDIO frame to the control register for a write cycle or MUXes out the content of the control register to the MDIO_GEM_I line for a read cycle.

Figure 2-8: Register Space Implementation
X-Ref Target - Figure 2-8

Table 2-5: Address 0x10: Core-Specific Control Register
Bits	Name	Default	Access	Description
15	Reset	0	R/W Self-clearing	1 = Resets the core and this register 0 = Normal operation
14	Reserved	0	R/W	Write as 0, ignore on read
13	Speed Selection (LSB)	0	R/W	6 13 1 1 = Reserved 1 0 = 1,000 Mb/s 0 1 = 100 Mb/s 0 0 = 10 Mb/s
12:9	Reserved	0	R/W	Write as 0, ignore on read
8:7	Reserved	0	R/W	Write as 0, ignore on read
6	Speed Selection (MSB)	0	R/W	6 13 1 1 = Reserved 1 0 = 1,000 Mb/s 0 1 = 100 Mb/s 0 0 = 10 Mb/s
5:0	Reserved	0x00	R/W	Write as 0, ignore on read

Table 2-6: Address 0x11: External PHY Address
Bits	Name	Default	Access	Description
15:5	Reserved	0x000	Reserved	Reserved
4:0	External PHY ID	0x1F	R/W	Provides the PHY ID of the External PHY

Table 2-7: Address 0x12: External PHY Status Register ID
Bits	Name	Default	Access	Description
15	AN Status Monitor Enable	0	R/W	Writing into this bit enables the snooping operation of the GMII to RGMII core for operation speed.
14:9	Reserved	0x00	Reserved	Reserved
8:5	AN Complete Bit Location	0x5	R/W	Position of AN Complete status bit in the 16 bit External PHY Status Register
4:0	External PHY Status Register ID	0x1	R/W	Register address of the External PHY Status Register

Table 2-8: Address 0x13: External PHY Status Register Contents
Bits	Name	Default	Access	Description
15:0	External PHY Status Register Contents	0x0000	R/O	Contents of the External PHY Status Register obtained during the last MDIO read from GEM by snooping the MDIO interface.

Table 2-9: Address 0x14: External PHY Speed Bit Register ID
Bits	Name	Default	Access	Description
15:5	Reserved	0x000	Reserved	Reserved
4:0	External PHY Speed Bit Register ID	0x1F	R/W	Register address of the External PHY Speed Register

Table 2-10: Address 0x15: External PHY Speed Bit Positions
Bits	Name	Default	Access	Description
15:12	Reserved	0x000	Reserved	Reserved
11:8	External PHY 10 Mb/s Speed Bit Position	0x2	R/W	Position of the 10 Mb/s speed resolved bit in the 16 bit wide External PHY Speed Register
7:4	External PHY 100 Mb/s Speed Bit Position	0x1	R/W	Position of the 100 Mb/s speed resolved bit in the 16 bit wide External PHY Speed Register
3:0	External PHY 1 Gb/s Speed Bit Position	0x0	R/W	Position of the 1 Gb/s speed resolved bit in the 16 bit wide External PHY Speed Register

Table 2-11: Address 0x16: External PHY Speed Bit Register Contents
Bits	Name	Default	Access	Description
15:0	External PHY Speed Bit Register Contents	0x0000	R/O	Contents of the External PHY Speed Register obtained during the last MDIO read from GEM after AN is complete by snooping the MDIO interface.