Port Changes from v2.0 to v3.0 - 4.1 English

clkin

Input

200 MHz Reference clock

This port is replaced by ref_clk_in. Map the 200/375 MHz clock from the shared logic block/external source to this port

mdio_mdc

Input

MDIO clock from GEM

This port is replaced by mdio_gem_mdc. Connect the GEM mdc port to this port.

mdio_i

Output

MDIO Input to GEM

This port is replaced by mdio_gem_i. Connect the GEM mdio_i port to this port.

mdio_o

Input

MDIO Output from GEM

This port is replaced by mdio_gem_o. Connect the GEM mdio_o port to this port.

mdio_t

Input

MDIO 3-state Input from GEM

This port is replaced by mdio_gem_t. Connect the GEM mdio_t port to this port.

mdc

Output

MDC clock to External PHY device

This port is replaced by mdio_phy_mdc. Connect the PHY MDC port to this port.

mdio

Bidirectional

MDIO data line to External PHY device

The core no longer instantiates the Bi-Di I/O primitive. Instead, it gives out the _i, _o, and _t signals, which should be connected to a Bi-Di I/O primitive. This primitive has to be user-instantiated.

ref_clk_in

Input

200 MHz clock from the shared logic block to the core

This should be driven by one of the following:

•the shared logic provided with the core

•by another cores shared logic block

•from another cores shared logic block

•from an external clock source

gmii_clk_125m_in

Input

Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0)

125 MHz GMII TX clock from the shared logic block to the core

This should be driven either by the shared logic provided with the core, or by another cores shared logic block.

gmii_clk_25m_in

Input

Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0)

25 MHz GMII TX clock from the shared logic block to the core

This should be driven either by the shared logic provided with the core, or by another cores shared logic block.

gmii_clk_2_5m_in

Input

Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0)

2.5 MHz GMII TX clock from the shared logic block to the core

This should be driven either by the shared logic provided with the core, or by another cores shared logic block.

mdio_phy_mdc

Output

MDC clock to External PHY device

Connect this to External PHY device MDC input.

mdio_phy_i

Input

The _o output from the Bi-Di primitive on the MDIO Data line from the External PHY Device

Connect this to the _o port of the Bi-Di I/O primitive on the MDIO to the External PHY device.

mdio_phy_o

Output

The _i input to the Bi-Di primitive on the MDIO Data line from the External PHY Device

Connect this to the _i port of the Bi-Di I/O primitive on the MDIO to the External PHY device.

mdio_phy_t

Output

The _t input to the Bi-Di primitive on the MDIO Data line form the External PHY Device

Connect this to the _t port of the Bi-Di I/O primitive on the MDIO to the External PHY device.