According to the RGMII v2.0 specification, the I/O pins must use 1.5V HSTL interface voltages. Like the majority of PHYs, those selected for Xilinx development boards are multi-standard and operate at either 1.8V or 2.5V.
A Tcl script that checks the I/O standard of RGMII is included with the IP and can be sourced post-implementation. The Tcl script is located at <project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/drc_check/io.
Table: I/O Standards Supported provides information on the I/O standards supported for different Zynq-7000 SoC devices that correspond to the Xilinx 7 series device programmable logic equivalent.