Features - 4.1 English

Core Specifics

Supported Device Family⁽¹⁾

Zynq^® UltraScale+™ MPSoC,

Zynq^®-7000 SoC,

Versal® device

Supported User Interfaces

GMII

Resources

Performance and Resource Utilization web page

Provided with Core

Design Files

Encrypted RTL

Example Design

GMII to RGMII with internally
generated GMII clock

GMII to RGMII with externally
generated GMII clock

Test Bench

Demonstration Test Bench

Constraints File

XDC

Simulation Model

Not Provided

Supported
S/W Driver

N/A

Tested Design Flows⁽²⁾

Design Entry

Vivado^® Design Suite

Simulation

For supported simulators, see the

Xilinx Design Tools: Release Notes Guide.

Synthesis

Vivado Synthesis

Support

Release Notes and Known Issues

Master Answer Record: 54689

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:

1.For a complete list of supported devices, see the Vivado IP catalog.

2.For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.