Demonstration Test Bench - 4.1 English

GMII to RGMII Product Guide (PG160)

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4.1 English

This Figure illustrates the demonstration test bench for the GMII to RGMII. The demonstration test bench is a simple VHDL program to test the core.

Figure 6-1:      GMII to RGMII Demonstration Test Bench

X-Ref Target - Figure 6-1


The test bench entity instantiates the example design for the core, which is the Device Under Test (DUT). The example design by itself is a wrapper around the core. The test bench entity contains stimulus, clocks, resets, and test bench semaphores. The test bench is located at <project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/simulation/demo_tb.vhd.

The demonstration test bench performs the following tasks:

Generates input clock signals.

Applies a reset to the example design.

Configures the GMII to RGMII core to operate at 1 Gb/s.

Injects four frames into the GMII transmitter from the GMII stimulus block.

Sets the first frame to the minimum length.

Sets the second frame as a type frame.

Sets the third frame as an errored frame.

Sets the fourth frame as a padded frame.

These steps are repeated for 100 Mb/s and 10 Mb/s speeds.