Internal Clocking - 4.1 English

GMII to RGMII Product Guide (PG160)

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4.1 English

This Figure illustrates the example design for top-level HDL when the GMII clock is sourced internally.

Figure 5-2:      Example Design HDL with Internal GMII Clock

X-Ref Target - Figure 5-2


In both examples, the design is split into two hierarchical layers: block-level and top-level. If shared logic is selected in the core, the top-level instantiates the block-level from HDL. Otherwise, it instantiates the support level. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

Instantiates the core from HDL

Connects the physical-side interface of the core to device IOBs, creating an external RGMII.

The top-level creates a specific example that can be simulated, synthesized, implemented, and, if required, placed on a suitable board and demonstrated in hardware.