Port Changes from v3.0 to v4.0 - 4.1 English

gmii_clk_90

Input

Present only when GMII clock is sourced externally (C_EXTERNAL_CLOCK = 1) and  clock skew is added though MMCM (RGMII_TXC_SKEW = 2). This is gmii_clk phase shifted by 90°.

This should be driven either by the shared logic provided with the core, or by another cores shared logic block.

gmii_clk_125m_90_in

Input

Present only when GMII clock is sourced internally

(C_EXTERNAL_CLOCK = 0) and  clock skew is added though MMCM (RGMII_TXC_SKEW = 2) 125 MHz GMII TX clock phase shifted by 90° from the shared logic block to the core

This should be driven either by the shared logic provided with the core, or by another cores shared logic block.

gmii_clk_25m_90_in

Input

Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) and clock skew is added though MMCM (RGMII_TXC_SKEW = 2) 25 MHz GMII TX clock phase shifted by 90° from the shared logic block to the core.

This should be driven either by the shared logic provided with the core, or by another cores shared logic block.

gmii_clk_2_5m_90_in

Input

Present only when GMII clock is sourced internally (C_EXTERNAL_CLOCK = 0) and clock skew is added though MMCM (RGMII_TXC_SKEW = 2) 2.5 MHz GMII TX clock phase shifted by 90° from the shared logic block to the core

This should be driven either by the shared logic provided with the core, or by another cores shared logic block.

mmcm_locked

Output

Valid only for Shared Logic in Core configuration and if the external clock option is not selected. This indicates that the MMCM has locked.

Can be left open if not used.