RGMII Interface Protocols - 4.1 English

GMII to RGMII Product Guide (PG160)

Document ID
Release Date
4.1 English

The RGMII is intended as an alternative to the IEEE Std 802.3-2012[Ref 2] Clauses 22 and 35 (MII) and Clauses 34–39, 41–42 (GMII), and the TBI. The principle objective is to reduce the number of pins required to connect the Ethernet MAC and the PHY from a maximum of 28 pins (TBI) to 12 pins in a cost-effective and technology-independent manner. To accomplish this objective, the datapaths and all associated control signals are reduced and control signals are multiplexed together, and both edges of the clock are used. For Gigabit operation, the clocks operate at 125 MHz, and for 10/100 operation, the clocks operate at 2.5 MHz and 25 MHz, respectively.