All ports in the encrypted hierarchy of the core are internal connections in FPGA logic.
Unencrypted HDL in the core and example design (delivered with the core) connects the GMII to RGMII core and adds IBUFs, OBUFs, and IOB flip-flops to the external signals of the core. IOBs are added to the remaining unconnected ports to run the example design using Xilinx implementation software.
All the ports described here indicate the pins in the encrypted hierarchy at the core level. The block-level design instantiates the core, clock selection logic, and shared logic if Include Shared Logic in Core is selected.