Block Hierarchy Level Ports - 4.1 English

tx_reset

Input

Active-High reset for TX Datapath.

rx_reset

Input

Active-High reset for RX Datapath.

clkin

Input

Valid only for Shared Logic in the Core configuration. This clock is used as the reference clock for the IDELAYCTRL elements and to clock the Management modules.

The frequency is set to 200 MHz for Zynq-7000 devices (for applicable frequencies, see Clock-Capable Clock Input Setup and Hold With MMCM table in Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics (DS187) [Ref 12] and Input/Output Delay Switching Characteristics table in Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics (DS191) [Ref 13]). The frequency is set to 375 MHz for Zynq UltraScale+ MPSoC devices. The frequency can be in the range of 300-800 MHz (see Input/Output Delay Switching Characteristics table in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)[Ref 14]). The frequency is set to 300 MHz for Versal device.

This clock is input to the MMCM when external clock mode is not enabled for generating 125/25/2.5 MHz clocks.

Note:   The MMCM settings are based on 200 MHz for Zynq-7000, 300 MHz for Versal device, and 375 MHz for Zynq UltraScale+ MPSoC. You are required to change the MMCM settings for any other frequencies.

ref_clk_out

Output

Valid only for Shared Logic in the Core configuration. This is a clkin signal passed through a BUFG and used to drive ref_clk_in for multiple instances of the core.

gmii_clk

Input

Valid only for Shared Logic in the Core configuration and if the external clock option is selected. The clock has a frequency of 125/25/2.5 MHz, depending on the speed selected.

gmii_clk_out

Output

Valid only for Shared Logic in the Core configuration and if the external clock option is selected. The clock is gmii_clk passed through a BUFG and is used to drive gmii_clk for multiple instances of the core.

gmii_clk_90

Input

gmii_clk phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

gmii_clk_90_out

Output

gmii_clk_out phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

gmii_clk_125m_out

Output

Valid only for Shared Logic in the Core configuration and if the external clock option is not selected. This 125 MHz clock is generated by MMCM from clkin.

gmii_clk_25m_out

Output

Valid only for Shared Logic in the Core configuration and if the external clock option is not selected. This 25 MHz clock is generated by MMCM from clkin.

gmii_clk_2_5m_out

Output

Valid only for Shared Logic in the Core configuration and if the external clock option is not selected. This 2.5 MHz clock is generated through clock division.

mmcm_locked_out

Output

Valid only for Shared Logic in the Core configuration and if the external clock option is not selected. This indicates that the MMCM has locked.

ref_clk_in

Input

Valid only for Shared Logic in the Example Design configuration. This signal is connected to the ref_clk_out signal of the core instance generated in the Shared Logic in the Core configuration.

gmii_clk_125m_90_out

Output

gmii_clk_125m_out phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

gmii_clk_25m_90_out

Output

gmii_clk_25m_out phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

gmii_clk_2_5m_90_out

Output

gmii_clk_2_5m_out phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

gmii_clk

Input

Valid only for Shared Logic in the Example Design configuration and if external clock option is selected. This signal is connected to the gmii_clk_out signal of the core instance generated in the Shared Logic in the Core configuration.

gmii_clk_125m_in

Input

Valid only for Shared Logic in the Example Design configuration and if external clock option is not selected. This signal is connected to the gmii_clk_125m_out signal of the core instance generated in the Shared Logic in the Core configuration.

gmii_clk_25m_in

Input

Valid only for Shared Logic in the Example Design configuration and if external clock option is not selected. This signal is connected to the gmii_clk_25m_out signal of the core instance generated in the Shared Logic in the Core configuration.

gmii_clk_2_5m_in

Input

Valid only for Shared Logic in the Example Design configuration and if external clock option is not selected. This signal is connected to the gmii_clk_2_5m_out signal of the core instance generated in the Shared Logic in the Core configuration.

gmii_clk_125m_90_in

Input

gmii_clk_125m_in phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

gmii_clk_25m_90_in

Input

gmii_clk_25m_in phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

gmii_clk_2_5m_90_in

Input

gmii_clk_2_5m_in phase shifted by 90°. This signal is valid only when 2 ns skew is added through MMCM.

mmcm_locked_in

Input

This signal is valid only when the external clock option is not selected for Shared Logic in the Example Design configuration. This is used in tx reset control.

speed_mode[1:0]

Output

See Table: I/O Signals for details about these signals.

gmii_tx_clk

Output

gmii_tx_en

Input

gmii_txd]7:0]

Input

gmii_tx_er

Input

gmii_crs

Output

gmii_col

Output

gmii_rx_clk

Output

gmii_rx_dv

Output

gmii_rxd[7:0]

Output

gmii_rx_er

Output

mdio_gem_mdc

In

mdio_gem_i

Output

mdio_gem_o

Input

mdio_gem_t

Input

link_status

Output

clock_speed[1:0]

Output

duplex_status

Output

rgmii_txd[3:0]

Output

rgmii_tx_ctl

Output

rgmii_txc

Output

rgmii_rxd[3:0]

Input

rgmii_rx_ctl

Input

rgmii_rxc

Input

mdio_phy_mdc

Output

mdio_phy_i

Input

mdio_phy_o

Input

mdio_phy_t

Input