Revision History

Versal Adaptive SoC AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2024-05-15
Revision
1.3 English

The following table shows the revision history for this document.

Section Revision Summary
05/15/2024 Version 1.3
AIE-ML Interfaces Updated the figure.
Memory-mapped AXI4 Interconnect Removed restrictions.
AIE-ML Array Reconfiguration Removed the Partial reconfiguration bullet.
11/10/2023 Version 1.2
Task-Completion-Tokens Added section.
Sparsity Added section.
02/15/2023 Version 1.1
Functional Overview Changed bullet under table from "Each of the two multipliers can be signed or unsigned." to "The multiplier multiplicand can be signed or unsigned."
AIE-ML Tile Architecture Added text regarding the memory tile being initialized to zero at boot and reset.
AIE-ML Memory Tile Overview and Features Added a bullet to the second list regarding the memory tile being initialized to zero at boot and reset.
AIE-ML Memory Tile Memory Updated both figures and added two notes.
Additional Resources and Legal Notices Added section.
09/28/2022 Version 1.0
Initial release. N/A