AIE-ML Array Interface

Versal Adaptive SoC AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2024-05-15
Revision
1.3 English

Similar to the Array interface in AIE, the AIE-ML array interface provides the necessary functionality to interface with the rest of the device. The array interface is made up of PL and NoC interface tiles, and there is one configuration interface tile per device. The following is a list of changes from the AIE array interface. The AIE-ML array interface has:

  • AIE-ML array interface DMA (read and write to external memory)
    • Supports 32-bit aligned start addresses
    • 3D address generation and iteration-state offset that supports, with a single buffer descriptor (BD) configuration, an incremental offset to be added to the base address with each subsequent transfer. Also supports 32-bit aligned addresses to external memory.
    • Task queue and task-complete-tokens
    • Support for S2MM out-of-order and Finish-on-TLAST features (enabling compressed spill and restore of intermediate results to external memory)
    • Task queues and task complete tokens
  • A lock design with 16 semaphore locks and 6-bit unsigned lock state
  • One stream FIFO (stream switch). This is a reduction from two in the AIE array interface.
  • Additional control and status registers for new features
  • Memory-mapped AXI4 interface for improved read and write bandwidth