AIE-ML Array Hierarchy

Versal Adaptive SoC AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2024-05-15
Revision
1.3 English

The AIE-ML array is made up of AIE-ML tiles, one or two rows of AIE-ML memory tiles, and AIE-ML array interface-tiles (the last row of the array). The following figure shows a conceptual view of the complete tile hierarchy associated with the AIE-ML array. See AIE-ML Tile Architecture, AIE-ML Array Interface Architecture, and AIE-ML Architecture for detailed descriptions of the various tiles.

Figure 1. Hierarchy of Tiles in an AIE-ML Array