AIE-ML Interfaces

Versal Adaptive SoC AIE-ML Architecture Manual (AM020)

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1.3 English
The AIE-ML has multiple interfaces. The following block diagram shows the interfaces.
Data Memory Interface
The AIE-ML can access data memory modules on all four directions. They are accessed as one contiguous memory. The AIE-ML has two 256-bit wide load units and one 256-bit wide store unit. From the AIE-MLs perspective, the throughput of each of the loads (two) and store (one) is 256 bits per clock cycle.
Program Memory Interface
This 128-bit wide interface is used by the AIE-ML to access the program memory. A new instruction can be fetched every clock cycle.
Direct AXI4-Stream Interface
The AIE-ML has one 32-bit input AXI4-Stream interfaces and one 32-bit output AXI4-Stream interfaces. There are no 128-bit stream interfaces and no FIFO connected to either input or output of the stream.
Cascade Stream Interface
The 512-bit accumulator data from one AIE-ML can be forwarded to another by using these cascade streams to form a chain. There is a small, two-deep, 512-bit wide FIFO on both the input and output streams that allow storing up to four values between AIE-MLs. In addition to the horizontal cascade, there is additional vertical cascade interface and the direction is controlled by the configuration memory-mapped AXI4 register.
Debug Interface
This interface is able to read or write all AIE-ML registers over the memory-mapped AXI4 interface.
Hardware Synchronization (Locks) Interface
This interface allows synchronization between two AIE-MLs or between an AIE-ML and DMA. The AIE-ML can access the lock modules in all four directions. There is also added support for semaphore locks.
Stall Handling
An AIE-ML can be stalled due to multiple reasons and from different sources. Examples include: external memory-mapped AXI4 master (for example, PS), lock modules, empty or full AXI4-Stream interfaces, data memory collisions, and event actions from the event unit.
AIE-ML Event Interface
This 16-bit wide EVENT interface can be used to set different events.
Tile Timer
The input interface to read the 64-bit timer value inside the tile.
Execution Trace Interface
A 32-bit wide interface where the AIE-ML generated packet-based execution trace can be sent over the AXI4-Stream.
Figure 1. AIE-ML Interfaces