Features of the AIE-ML Array Interface

Versal Adaptive SoC AIE-ML Architecture Manual (AM020)

Document ID
AM020
Release Date
2024-05-15
Revision
1.3 English
Memory Mapped AXI4 Interconnect
Provides functionality to transfer the incoming memory-mapped AXI4 requests from the NoC to inside the AIE-ML array.
AXI4 Master: Interface-DMA
Memory mapped access to the rest of the device via the NoC, including external memory.
AXI4-Stream Interconnect
Leverages the AIE-ML tile streaming interconnect functionality.
AIE-ML to PL Interface
The AIE-ML PL modules directly communicate with the PL. Asynchronous FIFOs are provided to handle clock domain crossing.
AIE-ML to NoC Interface
The AIE-ML to NoC module handles the conversion of 128-bit NoC streams into 32-bit AIE-ML streams (and vice versa). It provides the interface logic to the NoC components (NMU and NSU). Level shifting is performed because the NMU and NSU are in a different power domain from the AIE-ML.
Hardware Locks
Leverages the corresponding unit in the AIE-ML tile and is accessible from the AIE-ML array interface or an external memory-mapped AXI4 master, the module is used to synchronize the array interface to DMA transfer to/from external memory. The lock module has 16 semaphore locks and the lock state is 6-bit unsigned.
Debug, Trace, and Profile
Leverages all the features from the AIE-ML tile for local event debugging, tracing, and profiling.