The AIE-ML configuration process writes a programmable device image (PDI) produced by the bootgen tool into AIE-ML configuration registers. The AIE-ML configuration is done over memory-mapped AXI4 via the NoC. Any master on the NoC can configure the AIE-ML array. For more information on generating a PDI with the bootgen tool, refer to Bootgen User Guide (UG1283).
The AIE-ML array can be reconfigured at any time. The application drives the reconfiguration. Safe reconfiguration requires:
- Ensuring that reconfiguration is not occurring during ongoing traffic.
- Disabling the AIE-ML to PL interface prior to reconfiguration.
- Draining all data in the sub-region before it is reconfigured to prevent side-effects from remnant data from a previous configuration.
Complete reconfiguration is currently used to reconfigure the AIE-ML array. The global reset is asserted for the AIE-ML array and the entire array is reconfigured by downloading a new configuration image.
The PMC and PS are responsible for initializing the AIE-ML array. The following table summarizes the reset controls available for the global AIE-ML array.
Type | Trigger | Scope |
---|---|---|
Internal power-on-reset | Part of boot sequence | AIE-ML array |
System reset | NPI input | AIE-ML array |
INITSTATE reset | PCSR bit | AIE-ML array |
Array soft reset | Software register write over NPI | AIE-ML array |
AIE-ML tile column reset | Memory-mapped AIE-ML register bit in the array interface tile | AIE-ML tile column |
AIE-ML array interface reset | From NPI register | AIE-ML array interface tile |
The combination of column reset and array interface tile reset (refer to AIE-ML Array Hierarchy) enables a partial reconfiguration use case where a sub-array that comprises AIE-ML tiles and array interface tiles can be reset and reprogrammed without disturbing adjacent sub-arrays. The specifics of handling the array splitting and adding isolation depend on the type of use case (multi-user/tenancy or single-user/tenancy multiple-tasks).