The reg_dpu_reset register controls the resets of all DPUCZDX8G cores integrated in the DPUCZDX8G IP. The lower four bits of this register control the reset of up to four DPUCZDX8G cores. All the reset signals are active-High. The details of reg_dpu_reset are shown in the following table.
| Register | Address Offset | Width | Type | Description |
|---|---|---|---|---|
| reg_dpu_reset | 0x004 | 32 | R/W | [n] – DPUCZDX8G core n reset |