Data Controller Clock - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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3.4 English

The primary function of the data controller module is to schedule the data flow in the DPUCZDX8G IP. The data controller module works with m_axi_dpu_aclk. The data transfer between the DPUCZDX8G and external memory happens in the data controller clock domain, so m_axi_dpu_aclk is also the AXI clock for the AXI_MM master interface in the DPUCZDX8G IP. m_axi_dpu_aclk should be connected to the AXI_MM master clock.