Adding CE for dpu_2x_clk - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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3.4 English

The dpu_2x clock gating option can reduce the power consumption of the DPUCZDX8G. When the option is enabled, the number of generated clk_dsp should be equal to the number of DPUCZDX8G cores. Each clk_dsp should be set as a buffer with CE in the clock wizard IP. As shown in the following figure, three clk_dsp_ce appear when the output clock is configured with the CE. To enable the dpu_2x clock gating function, each clk_dsp_ce port should be connected to the corresponding dpu_2x_clk_ce port in the DPUCZDX8G.

Figure 1. Configure Clock Wizard with Buffer CE

After configuring the clock wizard, the clock_dsp_ce should be connected to the corresponding port in the DPUCZDX8G. The connections are shown in the following figure.

Figure 2. Clock CE and DPUCZDX8G Connections