Example System with the DPUCZDX8G - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
Release Date
3.4 English

The figure below shows an example system block diagram with the Xilinx® UltraScale+™ MPSoC using a camera input. The DPUCZDX8G is integrated into the system through an AXI interconnect to perform deep learning inference tasks such as image classification, object detection, and semantic segmentation.

Figure 1. Example System with Integrated DPUCZDX8G