|
Core Specifics |
| Supported Device Family |
Zynq®
UltraScale+™ MPSoC
Family |
| Supported User Interfaces |
Memory-mapped AXI interfaces |
| Resources |
See DPU Configuration. |
| Provided with
Core
|
| Design Files |
Encrypted RTL |
| Example Design |
Verilog |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Supported S/W Driver |
Included in PetaLinux |
| Tested Design
Flows |
| Design Entry |
Vivado® Design Suite and
Vitis™
unified software platform |
| Simulation |
N/A |
| Synthesis |
Vivado®
Synthesis |
|
Xilinx
Support web page
|
- Linux OS and driver support information are available from
DPUCZDX8G TRD or
Vitis™ AI development kit.
- For the supported tool versions, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- The DPUCZDX8G is driven
by instructions generated by the Vitis AI
compiler. When the target neural network (NN), DPUCZDX8G hardware architecture, or AXI data width is changed,
the related .xmodel file which contains DPUCZDX8G instructions must be regenerated.
|