Number of DPUCZDX8G Cores - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

Document ID
PG338
Release Date
2022-01-20
Version
3.4 English

A maximum of four cores can be selected in one DPUCZDX8G IP. Multiple DPUCZDX8G cores can be used to achieve higher performance. Consequently, it consumes more programmable logic resources.

Contact your local Xilinx sales representative if you require more than four cores.