Reference Clock Generation - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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3.4 English

There are three input clocks for the DPUCZDX8G and the frequency of dpu_2x_clk should be twice that of m_axi_dpu_aclk. m_axi_dpu_aclk and dpu_2x_clk must be synchronous. The recommended circuit design is shown here.

Figure 1. Reference Circuit

An MMCM and two BUFGCE_DIV blocks can be instantiated to design this circuit. The frequency of clk_in1 is arbitrary and the frequency of output clock CLKOUT in the MMCM should be the frequency of dpu_clk_2x. BUFGCE_DIV_CLK1_INST divides the frequency of CLKOUT by two. dpu_clk and dpu_clk_2x are derived from the same clock, so they are synchronous. The two BUFGCE_DIVs reduce the skew between the two clocks, which helps with timing closure.