Interrupts - 3.4 English

DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide (PG338)

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The DPUCZDX8G generates an interrupt to signal the completion of a task. A high state on reg_dpu0_start signals the start of a DPUCZDX8G task for DPUCZDX8G core0. At the end of the task, the DPUCZDX8G generates an interrupt and bit0 in reg_dpu_isr is set to 1. The position of the active bit in the reg_dpu_isr depends on the number of DPUCZDX8G cores. For example, when DPUCZDX8G core1 finishes a task while DPUCZDX8G core0 is still working, reg_dpu_isr would maintain 2’b10.

There will be DPU_NUM of dpux_interrupt signals for each of DPUCZDX8G cores. Theses signals shall be routed through a concat block, and then be connected to the PS. The reference connection is shown here.

Figure 1. Reference Connection for DPUCZDX8G Interrupt
  1. If the softmax option is enabled, then the softmax interrupt should be correctly connected to the PS according to the device tree description.
  2. irq7~irq0 corresponds to pl_ps_irq0[7:0].
  3. irq15~irq8 corresponds to pl_ps_irq1[7:0].