The following example shows a portion of an IPI Design with two AXI Traffic Generators and two
AXI block RAM Controllers along with associated embedded memory. This example is used to
show how you can adjust your datawidth and PL clock frequency to achieve the same
bandwidth. The axi_traffic_gen_64, axi_bram_ctrl_64,
and emb_mem_gen_64 all have 64-bit datawidths and connect to the 200
Mhz clock highlighted in green. The axi_traffic_gen_128,
axi_bram_ctrl_128, and emb_mem_gen_128 all have
128-bit datawidths and connect to the 100 Mhz clock highlighted in purple.
The axi_traffic_gen_64 has a connection through the NoC to the axi_bram_ctrl_64 while the axi_traffic_gen_128 has a connection through the NoC to the axi_bram_ctrl_128.
The required bandwidth for both read/write on each connection has been set to 1000 MB/sec on the NoC.
The initial NoC Solution after the design is validated in IPI is shown in the following figure and each NoC Connection is routed through the horizontal NoC.
The QoS Report (see the following figure) shows that the bandwidth requirements have been met and each connection is reporting a structural latency of 26 NoC Clock Cycles.
The NoC View in IPI allows for NMU/NSU assignment and the NoC solution can be updated to observe
the changes in the QoS Report. The axi_noc_0/inst/M01_AXI_nsu has been
moved in the NoC view away from the axi_noc_0/inst/S01_AXI_nmu to
create a longer path through additional NoC Switches. The resulting NoC view is shown in
the following figure.
For the resulting NoC QoS, the bandwidth has been maintained but the structural latency for the path has increased from 26 NoC clock cycles to 46 NoC clock cycles as shown in the following figure.
